Data Transfer Technique On 8085 Micro Controller

Data Transfer Technique 8085 Micro controller.

# What is Hardware Interrupt?

An external device is required for hardware interrupt and plugin on appropriate signal at interrupt pin of processor.

-8085 have five hardware interrupt pins

a] TRAP         b] RST 7.5    c] RST 6.5      d] RST 5.5     e] INTR 

TRAP

 It is a non-maskable interrupt i.e. it is not affected by any mask or interrupts enable. It has the highest priority. TRAP is edge & level triggered. This means the trap must go high & remain high until & it is acknowledged.

There are two ways to clear TRAP

•  BY resetting up
•   By giving a high TRAP Acknowledge signal

 # RST 7.5

• It interrupts that is mask able
• It has second-highest priority
• It is edge sensitive.
• Enabled by EI instruction

Ways to clear RST 7.5 interrupt

• System or process reset.
• By DI instruction

After a reorganization of interrupts.

# RST 6.5 & 5.5

• Both are level triggered
• It is also mask able interrupt
• Enable by EI instruction
• It is disabled or cleared by
• DI instruction
• System or process reset
• Reorganization of interrupts
• RST 6.5 has the third-highest priority and the RST 5.5 have the highest priority.

# INTR

•  It is also a mask able to interrupt.
•   Enable by EI instruction.
•   It is a non-recorded interrupt i.e. After receiving the INTA [Active low          signal it has to supply the address of ISR ]
•  It has the lowest priority.
•  Level sensitive
•  It is disabled by DI instruction.
•  Reset of the system,

– Reorganization of interrupts.

# Priority Interrupt control (PIC)

The INTR pin can be used for multiple peripheral and to determine the Priorities among the device the Plc is used. The recent device that is used for PIC is more versatile and advanced eg. PIC 8259A.

8259A  PIC Controller.

# Working of 8259A with microprocessor (8085)

• Frist 8259 should be programmed by sending the Installation command word (OCW) these commands will be in Form 8259 About.
•  Type of interrupt signal (level edge)
•  Type of processor
•  Call address and it’s interrupted.
•   masking.
•  Priority of interrupts.
•   Type of end of interrupts.
•  Once 8259 is programmed it is ready to accept the interrupt signal. When it receives the interrupt through any of the interrupt line IR₀-IR₇ it checks for its Priority its maskability
•   If the Previous interrupt is completed and if the current request have the highest Priority then it is served to the processer.
•  For servicing this interrupt 8259 will send INT Signal to INTR Pin of 8085.
•   In response it expects an acknowledge INTA (low) one by one.

interfacing 8259A with 8085

•  Now the running program address is saved to the stack register and the vector address of ꝋ interrupt is loaded on PC from where operation of the interrupt occurs
•  After completion of the interrupt RET signal is issued in order to return back to the main program for servicing.